RFIC II - Offered in Fall semester only

Course and Contact Information
Instructor: Sang-Soo Lee
Office Location: ENGR 259
Telephone: (408) 924-3950
Email: sang-soo.lee@sjsu.edu
Office Hours: MW 5:00 PM – 5:45 PM, Other time by appointment
Class Days/Time: MW 5:45 PM – 7:00 PM
Classroom: ENGR 343
Prerequisites: Graduate standing or instructor consent
 
Course Description
Low noise amplifiers, mixers, power amplifiers, LC voltage controlled oscillators, phase shifters, patch antennas and advanced layout to improve noise, stability, efficiency, and bandwidth performance of nanoscale CMOS integrated circuits. 

Course Format 
This course will be delivered in-person format. In certain circumstances, however, part of it will be delivered online through live zoom meeting, and the other part will be conducted asynchronously through the learning materials presented in the course Canvas.    

Course Learning Outcomes (CLO)
Students will acquire the ability to: characterize and model RF components, understand the operation of popular circuit architectures used in LNA, Mixer, VCO, PLL, Frequency Synthesizer, and PA. 

Upon successful completion of this course, students will acquire:
1.The ability to understand the RF components and their impact on the performance of the RF circuits 
2.The ability to understand methods and simulation tools to characterize complex RF integrated circuits
3.The ability to understand key requirements and calculate design parameters for LNA, Mixer, Oscillator, VCO, PLL, Frequency Synthesizer, and Power Amplifier circuits.
4.The ability to understand and model the loop characteristics and stability of PLL in Verilog-A and to design charge-pump PLL and Frequency Synthesizer circuits in transistor level implementation
5.The ability to verify the theory with hands-on Spectre RF circuit simulations
6.The ability to perform team work and analyze the operation of wireless transmitters and receivers

Required Texts/Readings 
Textbook
There is no required textbook. 
Other Readings
Lecture notes, slides, and technical papers will be posted in Canvas. The following references are recommended as supplementary readings. 
1.B. Razavi, RF Microelectronics, 2nd Edition, Upper Saddle River, New Jersey, Prentice Hall, 2012
2.T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge, U.K., Cambridge University Press, 2004.
3.Selected articles from IEEE publications. Papers can be downloaded from IEEE Xplore website. 

Other technology requirements / equipment / material 
Students are required to have a computer to run Cadence SpectreRF circuit simulator by connecting to the Cadence lab computer via VPN access. Students can come to the Cadence IC design lab (ENGR 289) if they want to or if they do not have the computer to run the Cadence software required for the course.  

Course Requirements and Assignments
Homework assignments and the final design project are mainly based on Cadence SpectreRF simulations and are closely related to the topics discussed in the class. Information on how to setup and run the Cadence simulation tools will be provided, and students are required to master this CAD tool by practicing Cadence tutorials provided by the instructor. The final design project requires extensive circuit simulation in Cadence and students must submit a formal project report to Canvas before deadline to be eligible to receive a credit. Non-restricted MOSFET transistor models will be provided for assignments and the project. More details on the design project will be provided as the lectures progress. 

 “Success in this course is based on the expectation that students will spend, for each unit of credit, a minimum of 45 hours over the length of the course (normally three hours per unit per week) for instruction, preparation/studying, or course related activities, including but not limited to internships, labs, and clinical practice. Other course structures will have equivalent workload expectations as described in the syllabus.”

Midterm and Final Examinations  
The date of the exams is shown on the course schedule section of the course syllabus. There will be no make-up exam and those absent will receive no credit. Students must write their answers clearly in an organized fashion and submit the answer sheets to Canvas. Further instructions on exam rule will be provided 2 weeks before the exams.

Grading Information
homework  15%
midterm exam  20%
design project  25%
final exam  40%

Determination of Grades
90% and above  A
89% - 85%  A minus
84% - 82%  B plus
81% - 79%  B
78% - 75%  B minus
74% - 72%  C plus
71% - 69%   C
68% - 65%  C minus
64% - 62%   D plus
61% - 59%  D
58% - 55%  D minus
below 55%  F

Classroom Protocol
Students will turn their cell phones off or put them on vibrate mode while in class. They will not answer their phones in the class. During the online class, students will mute themselves unless they need to speak for questions and answers.

Classroom Recording Policy
Students are not allowed to record (audio or video) in this class except in accordance with ADA accommodations. Students are not allowed to post class materials including videos in any other online site.

University Policies
Per University Policy S16-9 ,relevant university policy concerning all courses, such as student responsibilities, academic integrity, accommodations, dropping and adding, consent for recording of class, etc. and available student services (e.g. learning assistance, counseling, and other resources) are listed on Syllabus Information web page (https://www.sjsu.edu/curriculum/courses/syllabus-info.php). Make sure to visit this page to review and be aware of these university policies and resources.

Study Resources
SJSU has designated available classrooms for students to use for studying, attending online classes, and collaborating with other students. The 21 classrooms are located in buildings around the campus. In addition to the classrooms, study space is available in the King Library and Peer Connections.

A Study Resources (https://www.sjsu.edu/learnanywhere/campus-resources/study-resources.php) page has been added to the Campus Resources tab on the Learn Anywhere site to help students find these spaces.  The rooms are available August 19 through December 6, 2021. No reservations are required. The students can just go to the room, set themselves up, and start working.

EE Department Honor Code 
The Electrical Engineering Department will enforce the following Honor Code that must be read and accepted by all students. 

“I have read the Honor Code and agree with its provisions. My continued enrollment in this course constitutes full acceptance of this code. I will NOT: 
• Take an exam in place of someone else, or have someone take an exam in my place 
• Give information or receive information from another person during an exam 
• Use more reference material during an exam than is allowed by the instructor 
• Obtain a copy of an exam prior to the time it is given 
• Alter an exam after it has been graded and then return it to the instructor for re-grading 
• Leave the exam room without returning the exam to the instructor.” 

Measures Dealing with Occurrences of Cheating 
• Department policy mandates that the student or students involved in cheating will receive an “F” on that evaluation instrument (paper, exam, project, homework, etc.) and will be reported to the Department and the University. 
• A student’s second offense in any course will result in a Department recommendation of suspension from the University.

For More Information, contact:

Prof. Sang-Soo Lee at SJSU
sang-soo.lee@sjsu.edu